Signal skew poses many concerns in high speed data processing environments. By "skew", what is meant is a time shift in a signal, generally relative to a clock or other signal, which results in the transitions between individual data bits in a digital signal stream which are offset in time from the transitions in the clock.
A signal may be skewed, or out of alignment, relative to another signal either between individual integrated circuit chips, or within different areas of the same chip. This often occurs due to signal propagation delays along transmission lines and through integrated circuitry. A skewed signal poses a concern because it may result in errors due to missed data or register ripple-through. Often, to account for skew, one or more "wait states", or full clock cycles, may be added to a signal to ensure that the data is valid. However, the insertion of wait states into signals slows down processing and results in a slower information transfer.
Signal skew is conventionally handled in two manners. First, signal skew between different integrated circuit chips may be handled by low skew clock distribution networks. Often the skew between different chips is due to different transmission line lengths between a common signal source and the chips. This form of skew is often handled by making the signal lengths between the chips and the signal source the same, and/or by measuring the delays to the different chips and compensating for the delays using phase locked loops or inserted delays. However, it has been found that feedback systems for measuring and compensating for transmission delays may also introduce some skew. In addition, many of these systems do not account for signal propagation delays through the chips themselves.
Second, signal skew may be handled through internal chip clock synchronization to align signals throughout a chip. For example, one particular application which requires low skew signals is a memory controller, which coordinates data transfers to and from one or more memory devices across a bus. Memory controllers typically provide control signals to control the memory devices to receive or transmit data across the bus, for example to a processor or other controlling or peripheral devices.
The control signals generated by a conventional memory controller, however, often have at least some skew relative to the system clock which drives the bus. This is because some logic components are always downstream of a clock input when producing output signals in a chip, often resulting in a minimum of about 7-10 nanoseconds of skew. Often, conventional memory controllers must insert one or more wait states into the control signals to handle the access delays associated with the memory devices.
Further, as memory systems get faster, skew becomes more significant relative to the clock cycle, and the risk of errors increases. For example, memory devices such as DRAMs are capable of operating at 66 MHz or more (i.e., with 15 ns clock cycles). Other memory devices such as SRAMs may run even faster. With conventional memory controllers providing a minimum of 7-10 nanoseconds of skew in the control signal, the skew in the control signals may thus represent up to 67% of the total clock cycle.
Synchronous DRAMs are another option for minimizing control signal skew relative to a bus, as they receive a system clock directly and use the clock to gate control signals from a memory controller. This typically minimizes the propagation delay downstream of the gates in the memory devices, thereby minimizing the skew of the control signals. However, synchronous DRAMs are often not particularly desirable because space on memory devices is very expensive both economically and performance-wise, so any additional control circuitry on a memory device is generally discouraged.
Therefore, a substantial need exists for a memory controller which is capable of generating low skew control signals to control memory devices.
In addition, we have found that a unique concern exists with regard to signal skew in applications which utilize memory devices having enhanced memory transfer modes such as page mode and extended data out (EDO) mode, where memory addresses located within the same page or column of a memory device may be transferred without having to repeatedly send full address information to the device for each memory location. In particular, we have found that the higher operating speeds and enhanced operating modes of many memory devices are beyond the capabilities of many conventional memory controllers. Since less delay is required when accessing multiple addresses in such memory devices, wait states, or slower transfer rates, are often the only available alternatives for many conventional memory controllers.
Therefore, in view of our realization of the inadequacy of conventional memory controllers in handling the particular concerns associated with the use of high speed memories operating in enhanced transfer modes, a substantial need has also arisen for a memory controller which is capable of generating low skew control signals to control such high speed enhanced mode devices.